1. Field of the Invention
This invention relates generally to the field of information storage, and more particularly to hard disk drive magneto-resistive head preamplifiers.
2. Description of the Prior Art
The need for larger and faster mass storage devices continues to increase as computer hardware and software technology continues to progress. Electronic databases and computer applications such as multimedia applications, for example, require ever increasing amounts of disk storage space.
Hard disk drive (HDD) technology continues to evolve and advance in order to meet these ever increasing demands. U.S. Pat. No. 5,831,888, entitled Automatic Gain Control Circuit, and assigned to Texas Instruments Incorporated, the assignee of the present invention, sets forth generally the description of disk storage and is incorporated by reference herein in its entirety. An HDD performs write, read and servo operations when storing and retrieving data. During a read operation, the appropriate hard disk sector to be read is located and data that has been previously written to the disk is read. A read/write head senses the changes in the magnetic flux of the disk platter and generates a corresponding analog read signal. A read channel receives the analog read signal, conditions the signal and detects xe2x80x9czerosxe2x80x99 and xe2x80x9conesxe2x80x9d from the signal.
Hard disk drives are one type of disk storage that are particularly used in modem personal computers. A HDD device generally includes a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a preamplifier, a read channel, a write channel, a servo controller, a memory, and control circuitry to control the operation of the HDD and to properly interface the HDD to a host or system bus.
FIG. 1 illustrates a well known disk/head assembly 12 and a preamplifier 14. The preamplifier 14 handles both read functions and write functions. Not illustrated in FIG. 1, for clarity, is the Magneto-resistive (MR) head that connects to the preamplifier 14. An MR head works through magnetic media, using a different portion of the head to perform either a read or a write function. The write function portion of the MR head is inductive while the read function portion of the head acts as a magneto-resistive element to sense magnetic shifts in the disk assembly 12.
FIG. 2 is a simplified schematic diagram illustrating a well known portion of a read channel circuit suitable for use with the preamplifier 14 shown in FIG. 1.
Resistors RMR1-RMR6 represent the resistive portion of six MR heads. An input amplification stage 18 of preamplifier 14 connects to the resistive portion, RMR1-RMR6 of the MR heads. Later gain stages 20 of preamplifier 14 are connected to the outputs of input amplification stage 18 at nodes NA and MB. The read path outputs flow from the later gain stages 20. The read channel inputs flow into preamplifier 14 from a head select logic stage. Preamplifier 14 may have as many as one to more than eight channels in typical HDD devices. Transistor SW1 represents the read channel input enabling MOS transistor for head one of the six heads illustrated in FIG. 2. The other enabling MOS transistors for heads two through six are not illustrated to preserve clarity. Head one is illustrated as the selected head, while the remaining five heads are illustrated in the off condition with the respective bases of input NPN transistors Q2-Q6 being connected to the integrated circuit ground.
The architecture of input amplification stage 18 of preamplifier 14 can be seen to be formulated as a single ended amplifier having a single transistor Q11 to set the voltage level on the load side of later gain stage 20. A differential amplifier, as is known to one of ordinary skill in the art of amplifier design, uses two transistors to establish the voltages on nodes N and M. A bias current IB travels through the load resistor RL and through the collector of transistor Q11 to set the voltage level on node M. A bias current IB/xcex1 passes through a scaling resistor 20RL to set a reference voltage level on node N. The read head is generally biased at about 0.2 to about 0.5 volts to improve linearity characteristics during a read operation. This read head bias voltage is established via a feedback loop created by transconductance amplifier 22 across nodes M and N such that the amplifier 22 output is connected to the base of transistor Q1 through MOS switch SW1. This structure creates a pseudo-balanced output on the reader load resistors RL and 20RL such as would exist if a differential amplifier were used in the input amplification stage.
NPN bipolar transistors Q11 and Q1 are active when head one is selected. Together with the load resistor RL, Q11 and Q1 form a cascade amplifier. A cascade amplifier is a high bandwidth amplifier suitable for processing data at high speeds on the order of Mbits/sec. Both Q11 and Q1 are configured as common base amplifiers. As a magneto-resistive (MR) head moves over data, the head resistance RMRX varies much like an alternating current signal in series with the head resistance RMRX. The NPN bipolar transistors Q11 and Q1 amplify a signal proportional to this variation in head resistance RMRX. This amplified ac signal is passed through the load resistor RL and into the base of emitter follower transistor Q8. The amplified ac signal then passes on to node MB that forms one input of the later gain stage 20 that is configured as a differential amplifier. The second input of the amplifier 20 is node NA that is set to be at a dc bias voltage equal to the voltage on the node MB. Ideally, the node NA should not have an alternating current signal passing through it. Thus, the reference side of the single ended input amplification stage 18 consists of transistors QB, Q21 and the scaling resistor 20RL. This structure supplies a current IB/xcex1 through the scaling resistor 20RL, that provides a reference voltage at node N. Those skilled in the art will readily appreciate that if the dc voltage on nodes M and N are the same, then the input voltage on differential amplifier 20 at nodes NA and MB are the same. Thus, only node MB will see an ac signal. Because the dc voltages are equal in magnitude, the differential amplifier 20 will amplify only the ac signal and send it onto later gain stages.
FIGS. 3A and 3B show a more detailed schematic diagram illustrating a known architecture for a HDD read circuit MR head preamplifier 100 having a bipolar transistor differential amplifier structure and that is generally used for processing digital data at speeds up to about 1.6 Mbits/sec. These figures shall be used herein after to more particularly describe limitations associated with presently known preamplifier architectures. Looking now at FIG. 3A, the resistors RRM1-RMX represent the variable head resistance associated with each respective magneto-resistive (MR) head. The following operating principles, although described with reference to resistor RRM1, apply equally to each MR head. A read signal generated via RRM1 is first amplified by a cascade amplifier formed by transistors Q12 and Q110 as well as load resistor RL depicted in stage 1 of FIG. 3A. The amplified read signal thus appears across load resistor RL. The signal across load resistor RL is applied to an emitter follower amplifier formed by bipolar transistor Q16, also shown in stage 1. Following amplification of the read signal via transistor Q16, the amplified read signal is then passed to a differential amplifier comprising bipolar transistors Q21, Q22, Q23 and Q24 illustrated in stage 2. Although further amplification and signal processing takes place in stage 3 of the MR head preamplifier 100, this amplification and signal processing is not relevant to the present discussion. Therefore, discussion of the amplification and signal processing that takes place in stage 3 will not be discussed herein to preserve clarity. The MR head preamplifier 100 thus comprises a plurality of variable head resistances RRM1-RMX, associated cascade amplifiers, emitter follower amplifiers and a differential amplifier, operationally and structurally similar to the corresponding elements of preamplifier 14 illustrated in FIG. 2 and discussed herein before.
A plurality of interrelated circuit properties adversely affect the bandwidth characteristics of the preamplifier 100. The useable bandwidth, for example, of the preamplifier 100 is significantly affected by the pole(s) created by the loading caused by the cascade amplifier bipolar transistors Q12, Q13 and so forth, as well as emitter follower amplifier transistor Q16, on the load resistor RL. The loading characteristics of cascade amplifier bipolar transistors Q12, Q13 and so on as well as emitter follower amplifier transistor Q16 created at the load resistor RL are determined in part by the parasitic capacitances, e.g. collector-base, emitter-base, associated with each transistor.
Further, the noise properties associated with the preamplifier 100 are adversely affected by thermal noise contributions from cascade bipolar transistors Q110 and Q111 among others. Undesirable thermal noise is additionally generated by emitter follower amplifier transistor Q16 as well as differential amplifier transistors Q21 and Q22.
Recent advancements associated with HDD technology have made it desirable if not even necessary to further reduce noise associated with MR read head preamplifiers. Such noise reductions can be useful in formulating MR read head preamplifiers having very wide useable bandwidths essential for accommodating data processing speeds of more than 300 Mbits/sec. In view of the foregoing, it is desirable to provide a MR read head preamplifier having significantly reduced thermal noise and reduced capacitive loading characteristics such that data can be reliably processed via the preamplifier at speeds up to 320 Mbits/sec or even higher.
The present invention is directed to a HDD read head preamplifier architecture having a xe2x88x921 dB bandwidth of about 160 MHz and that is suitable for use with hard disk drives with data rates up to about 320 Mbits/sec without sacrificing desirable read head current range properties. One embodiment of the present preamplifier 200 architecture comprises a common node that couples a plurality of read heads, i.e. resistors RMR1-MRX, to a load resistor RL via a single shared common base amplifier. The resultant preamplifier architecture therefore does not suffer any degradation in bandwidth characteristics generally associated with dominant poles created using known preamplifier architectures where a large parasitic capacitance associated with multiple cascade amplifiers is coupled with a large load resistance to generate unwanted dominant poles. The shared common base amplifier replaces the more classic emitter follower amplifier that is generally used in the art to formulate the first preamplifier stage. Therefore, the dominant pole contributions generally associated with known first stage emitter follower amplifier architectures are effectively eliminated or substantially reduced since the familiar emitter follower architecture has also been replaced with a common base architecture. The read signal output from the common base amplifier is passed to a differential amplifier transistor pair where a pair of cross-coupled bipolar transistors are configured to substantially reduce or eliminate parasitic collector-base capacitance associated with the differential amplifier transistors. The present preamplifier architecture produces lower noise levels and greater useable bandwidth than that achievable by using HDD read head architectures presently known in the art.
The present invention thus provides various technical advantages. In one aspect of the invention, a HDD magneto-resistive read head preamplifier architecture is provided that eliminates or substantially reduces dominant poles caused by parasitic capacitance loading associated with a preamplifier input stage load resistor.
In another aspect of the invention, a HDD read head preamplifier structure is provided that substantially reduces noise levels generally associated with known read head preamplifier architectures.
In yet another aspect of the invention, a HDD read head preamplifier structure is provided that substantially improves the xe2x88x921 dB bandwidth characteristics generally associated with known read head preamplifier architectures.
In still another aspect of the invention, a HDD read head preamplifier structure is provided that substantially improves the xe2x88x921 dB bandwidth properties generally associated with known read head preamplifier architectures without sacrificing read head current range capabilities.
In another aspect of the invention, a HDD read head preamplifier structure is provided that functions with a larger value of load resistance than that generally associated with known read head preamplifier architectures, thereby providing reduced preamplifier generated noise and improved operating stability.
In yet another aspect of the invention, a HDD read head preamplifier structure provides improved noise characteristics sufficient to reduce error rates about an order of magnitude over that generally associated with known read head preamplifier structures.
In still another aspect of the invention, a HDD read head preamplifier structure provides a noise gain of about 10% over a xe2x88x921 dB bandwidth of about 160 MHz while retaining desired read head current range characteristics.